Instruction Pipeline, Register Allocation, Branch Prediction, Mobile Computing

3rd Largest Element: SIMD Edition
parallelprogrammer.substack.com·15h·
Discuss: Substack
SIMD Optimization
PIPER Robotic Arm - Fixed Position Recording & Replay
hackster.io·1d
🤖Tape Automation
AAEON GENE-ARH6 – A 3.5-inch subcompact industrial SBC with Intel Core Ultra 200H/U SoC
cnx-software.com·5h
🖥️Hardware Architecture
3D nesting / 3D Packing
github.com·2h·
🧮Z3 Applications
Q3 2025 Major Release is now available
msab.com·1h
📚MARC Archaeology
ARM loses across the board to Qualcomm
heise.de·1h
🦾ARM Cortex-M
Make the most of compiled C loops on the 68000
dciabrin.net·2d·
Discuss: Hacker News
🎮Game Decompilation
Linus Torvalds Lashes Out At RISC-V Big Endian Plans
phoronix.com·17m
🧪RISC-V Fuzzing
Sguaba: Type-safe spatial math in Rust
youtube.com·1d·
🦀Rust Borrowing
Native Python Packaging: BLAS, Lapack and OpenMP
pypackaging-native.github.io·4h·
Discuss: Hacker News
Homebrew CPUs
Anomaly detection for generic failure monitoring in robotic assembly, screwing and manipulation
arxiv.org·8h
👁️System Observability
Materializing
blog.supermechanical.com·16h
⚙️DIY Electronics
Using the TPDE Codegen Back End in LLVM Orc
weliveindetail.github.io·1d·
Discuss: Hacker News
🏭Compiler Backends
Revolutionizing Data Cloud: Unleashing the Power of the New ML Recommendations System
engineering.salesforce.com·20h
🏠Homelab Orchestration
#051: A Neat Little Rcpp Trick
dirk.eddelbuettel.com·21h
🎯Gradual Typing
Long-context LLMs in the wild: A hands-on tutorial on Ring Attention
akasa.com·20h·
Discuss: Hacker News
Cache Coherence
Register allocation in the Go compiler
vnmakarov.github.io·4d·
🚀Compiler Optimizations
On-Device AI Agents in Production: Privacy, Performance, and Scale // Varun Khare & Neeraj Poddar // #340
podcasters.spotify.com·20h
🤖AI Curation
Intel's original 64bit extensions for x86
soc.me·1d·
Discuss: r/programming
🧲RISC-V Archaeology